Coarse-grained reconfigurable array architectures

Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. By executing non-loop code on other cores, however, CGRAs can focus on such loops to execute them more efficiently. This chapter discusses the basic principles of CGRAs, and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code

Policy-Driven Memory Protection for Reconfigurable Hardware

Abstract. While processor based systems often enforce memory pro-tection to prevent the unintended sharing of data between processes, current systems built around reconfigurable hardware typically offer no such protection. Several reconfigurable cores are often integrated onto a single chip where they share external resources such as memory. While this enables small form factor and low cost designs, it opens up the op-portunity for modules to intercept or even interfere with the operation of one another. We investigate the design and synthesis of a memory protection mechanism capable of enforcing policies expressed as a formal language. Our approach includes a specialized compiler that translates a policy of legal sharing to reconfigurable logic blocks which can be di-rectly transferred to an FPGA. The efficiency of our access language design flow is evaluated in terms of area and cycle time across a variety of security scenarios

DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems

. Current simulation tools for reconfigurable systems are based on low level simulation of application designs developed in a High-level Description Language(HDL) on HDL models of architectures. This necessitates expertise on behalf of the user to generate the low level design before performance analysis can be accomplished. Most of the current simulation tools also are based on static designs and do not support analysis of dynamic reconfiguration. We propose a novel interpretive simulation and visualization environment which alleviates these problems. The Dynamically Reconfigurable systems Interpretive simulation and Visualization Environment(DRIVE) framework can be utilized for performance evaluation and architecture and design space exploration. Interpretive simulation measures the performance of an application by executing an abstract application model on an abstract parameterized system architecture model. The simulation and visualization framework is being developed in Java lan..

Mapping Loops onto Reconfigurable Architectures

Reconfigurable circuits and systems have evolved from application specific accelerators to a general purpose computing paradigm. But the algorithmic techniques and software tools are also heavily based on the hardware paradigm from which they have evolved. Loop statements in traditional programs consist of regular, repetitive computations which are the most likely candidates for performance enhancement using configurable hardware. This paper develops a formal methodology for mapping loops onto reconfigurable architectures. We develop a parameterized abstract model of reconfigurable architectures which is general enough to capture a wide range of configurable systems. Our abstract model is used to define and solve the problem of mapping loop statements onto reconfigurable architectures. We show a polynomial time algorithm to compute the optimal sequence of configurations for one important variant of the problem. We illustrate our approach by showing the mapping of an example loop statement

Dynamic Precision Management for Loop Computations on Reconfigurable Architectures

Reconfigurable architectures promise significant performance benefits by customizing the configurations to suit the computations. Variable precision for computations is one important method of customization for which reconfigurable architectures are well suited. The precision of the operations can be modified dynamically at run-time to match the precision of the operands. Though the advantages of reconfigurable architectures for dynamic precision have been discussed before, we are not aware of any work which analyzes the qualitative and quantitative benefits which can be achieved. This paper develops a formal methodology for dynamic precision management. We show how the precision requirements can be analyzed for typical computations in loops by computing the precision variation curve. We develop algorithms to generate optimal schedules of configurations using the precision variation curves. Using our approach, we demonstrate 25%-37% improvement in the total execution time of an example..

Reconfigurable Computing: Architectures, Models and Algorithms

The performance requirements of applications have continuously superseded the computing power of architecture platforms. Increasingly larger number of transistors available on a chip have resulted in complex architectures and integration of various architecture components on the chip. But, the incremental performance gains obtained are lower as the complexity and the integration increase. Reconfigurable architectures can adapt the behavior of the hardware resources to a specific computation that needs to be performed. Computing using reconfigurable architectures provides an alternate paradigm to utilize the available logic resources on the chip. For several classes of applications, reconfigurable computing promises several orders of magnitude speed-up compared to conventional architectures. This article provides a brief insight into the architectures, models and algorithms which facilitate reconfigurable computing. 1 Introduction Microprocessors are at the heart of most curr..

Loop Pipelining and Optimization for Run Time Reconfiguration?

Lack of automatic mapping techniques is a signi cant hurdle in obtaining high performance for general purpose computing on reconfigurable hardware. In this paper, we develop techniques for mapping loop computations from applications onto high performance pipelined configurations. Loop statements with generalized directed acyclic graph dependencies are mapped onto multiple pipeline segments. Each pipeline segment is executed for a fixed number of iterations before the hardware is reconfigured at runtime to execute the next segment. The reconfiguration cost is amortized over the multiple iterations of the execution of the loop statements. This alleviates the bottleneck of high reconfiguration overheads in current architectures. The paper describes heuristic techniques to construct pipeline configurations which have reduced total execution time including the runtime reconfiguration overheads. The performance benefits which can be achieved using our approach are illustrated by mapping example application loop onto Virtex series FPGA from Xilinx

Hardware Object Selection for Mapping Loops onto Reconfigurable Architectures

Reconfigurable circuits and systems have evolved from application specific accelerators to a general purpose computing paradigm. Reconfiguring the logic is still an expensive operation and precludes frequent configuration changes. To reduce the overheads involved in reconfiguration, devices with configuration caches and multiple contexts are being designed. Reconfigurable computing solutions are typically designed by composing lower level modules or library components. Each operation in an application can be implemented by using any one among several of these modules or hardware objects. This gives rise to the problem of choosing an optimal set of modules for utilizing the cache or the multiple contexts. This paper develops a formal methodology for selection of these modules to minimize the total execution time. The total execution time includes the reconfiguration time and the computation time in various configurations. We focus on loop computations since they are the most compute int..